The present invention relates generally to electronic devices, and more particularly to memory management systems used in such devices.
In conventional multi-core systems, each core (processing unit) has an associated tightly coupled memory (TCM) that may be a cache memory. FIG. 1 shows a system 50 having two cores 10, 20 as known in the prior art. Core 10 directly communicates with a dedicated data cache 14 and a dedicated instruction cache 12. Core 20 directly communicates with a dedicated data cache 24 and a dedicated instruction cache 22. Because data cache 14 and instruction cache 12 are dedicated to core 10, these two caches are not accessible to core 20. Similarly, because data cache 24 and instruction cache 22 are dedicated to core 20, these two caches are not accessible to core 10. Cores 10 and 20 are typically configured to execute common instructions. Storing such common instructions in both instruction caches 12 and 22 result in inefficiencies. Similarly, cores 10 and 20 may operate on the same data and, therefore, inefficiencies result from having dedicated data caches.